Embedded semiconductor device substrate and production method thereof

ABSTRACT

An embedded semiconductor device substrate having a semiconductor device integrated therein is formed by disposing a semiconductor device in an opening provided on an insulating resin, and sandwiching the semiconductor device and the insulating resin with a front surface wiring layer and a rear surface wiring layer and performing heat pressing. Connection between bumps of the semiconductor device and the front surface wiring layer is made with a connection wiring pattern. The connection wiring pattern is formed by patterning a resist film by direct exposure thereof with a light beam, and then performing etching. Thereby, it becomes possible to absorb a mounting error of a semiconductor device to a printed wiring board and a positional error of electrodes between semiconductor devices accompanying the tendency of reduction of the pitch of a semiconductor device, and to perform electric connection with a wiring pattern securely.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an embedded semiconductor devicesubstrate having a semiconductor device buried in an insulating resinlayer of a printed wiring board, and a method of producing the same.

2. Description of the Related Art

In recent years, the semiconductor package having a semiconductor devicemounted therein has been continuously reduced in size and weight.Therefore, there has been increasing adopted a structure in which anelectrode portion of a semiconductor package is formed into an areaarray, such as BGA (Ball Grid Array) and CSP (Chip Scale Package).

Furthermore, not only a two-dimensional size reduction such as the BGAand CSP, but also a multi chip package in which a plurality ofsemiconductor devices are stacked in a single package has been proposedsuch as disclosed in Japanese Patent Application Laid-Open No. H11-3970.

On the other hand, in addition to such size reduction of semiconductorpackages, an embedded semiconductor device substrate having asemiconductor device buried inside of a printed wiring board has beenproposed such as disclosed in Japanese Patent Application Laid-Open No.H09-321408. In the embedded semiconductor device substrate disclosed inJapanese Patent Application Laid-Open No. H09-321408, a semiconductordevice having stud bumps formed thereon is mounted in a recessed portionformed beforehand on a printed wiring board, and an insulating layer isthen formed so as to cover the semiconductor device.

However, in the embedded semiconductor device substrate described inJapanese Patent Application Laid-Open No. H09-321408, since a routeringis necessary for forming a recessed portion in a printed wiring board,which increases the processing time remarkably. In addition, in order tobury a semiconductor device, it is necessary to form a holding surfacefor holding the semiconductor device at a bottom of the recessedportion, and an insulating layer is needed for the holding surface. Inconsequence, the thickness of the embedded semiconductor devicesubstrate having the semiconductor device varied therein becomes verylarge, which makes the size reduction difficult.

So, there has been proposed a method which does not form a recessedportion beforehand in a printed wiring board but buries a semiconductordevice during production of a printed wiring board to thereby produce anembedded semiconductor device substrate, in Japanese Patent ApplicationLaid-Open No. 2004-335641. The production method disclosed therein willbe explained with reference to FIGS. 10A to 10F.

First, as shown in FIG. 10A, a semiconductor device 101 is mountedthrough an insulating epoxy resin 104 on a Cu foil 103. Next, as shownin FIG. 10B, a prepreg material 105 is disposed at such a location thatan opening 105 a of the prepreg materiel 105 contains the semiconductordevice 101. The prepreg material 105 has approximately the samethickness as the thickness of the semiconductor device 101, and theopening 105 a having a shape corresponding to the shape of thesemiconductor device 101 is formed with a punching press. In addition,on the prepreg material 105, there is put an RCC (Resin Coated Cupper)material 107 having an epoxy resin 106 as an insulating resin coated ona Cu foil 103 a. The Cu foil 103, prepreg material 105, and RCC material107 (epoxy resin 106/cupper foil 103 a) are disposed by stacking in thisway, and are subjected to thermocompression bonding in a vacuumatmosphere as shown in FIG. 10C.

Next, as shown in FIG. 1D, a part of the Cu foil 103a corresponding toan electrode portion 102 on the semiconductor device 101 is removed byordinary etching to form a hole portion. Then, a part of the epoxy resin106 which is exposed via the hole portion is removed by a laser such asa CO₂, YAG, or excimer laser to form an opening 108, whereby theelectrode portion 102 of the semiconductor device 101 is exposedtherethrough. Next, as shown in FIG. 12E, while a Cu layer 103 b isformed on the entire surface by plating, the opening 108 is filled withthe Cu layer 103 b.

Subsequently, a resist material is coated on the Cu layer 103 b, and awiring pattern is formed in an exposure step through a mask and adevelopment step, so that the embedded semiconductor device substratehaving the semiconductor device 101 integrated therein as shown in FIG.10F is obtained.

In the embedded semiconductor device substrate disclosed in JapanesePatent Application Laid-Open No. 2004-335641 above, by forming anopening accurately by use of a laser, electrodes of a semiconductordevice are exposed outside. Furthermore, by etching a Cu layer formed ona printed wiring board by use of a mask, a wiring pattern connected tothe electrodes is formed. Hence, there is required an etching accuracyof such an extent as to surely connect the electrodes of thesemiconductor device and the wiring pattern on the printed wiring boardto each other.

On the other hand, since a large number of semiconductor devices areproduced from a single semiconductor wafer, there are differencesbetween individual semiconductor devices obtained therefrom, and thereare positional errors between the individual semiconductor devices alsowith regard to electrode positions. Furthermore, there will benecessarily generated a mounting error within a predetermined range inthe mounting position of a semiconductor device to a printed wiringboard. Therefore, there is generated a displacement with respect to adesign position between the patterning position of a wiring pattern, andthe position of an electrode of a semiconductor device. Generally, inprospect of this displacement, the patterning using a mask is made so asto provide a pattern shape with a predetermined amount of margin.

Nevertheless, as the pitch of electrodes of a semiconductor device isreduced, it becomes impossible to take a sufficient margin to avoidinterference with an adjacent wiring pattern. That is, it becomesdifficult to allow the above described errors when mountingsemiconductor devices to a printed wiring board and positional errors ofelectrodes between individual semiconductor devices, by means of amargin of a pattern shape. Thereby, the electrodes of the semiconductordevices and the wiring on the printed wiring board will not beconnected. Such a situation becomes significant as the pitch betweenelectrodes of a semiconductor device is reduced, and it is believed thatit will become a more serious problem in the future.

SUMMARY OF THE INVENTION

Therefore, the present invention has been accomplished in view of suchproblems, and it is an object of the present invention to provide anembedded semiconductor device substrate, which can increase thestability of electric connection to a wiring pattern, corresponding tothe tendency of reduction in pitch of an electrode portion of asemiconductor device, and a method of producing the same.

According to a first aspect of the present invention, there is providedan embedded semiconductor device substrate having a semiconductor deviceintegrated in an insulating resin layer, wherein a wiring pattern isformed on the insulating resin layer, a bump for connection is formed onan electrode portion on the semiconductor device, and the wiring patternand the bump are connected through a connection wiring pattern providedon the wiring pattern and the bump.

In the present invention, it is preferred that the connection wiringpattern is thinner than the wiring pattern.

Further, it is preferred that the wiring has a multi-layer structurewhich is comprised of a plurality of materials.

According to a second aspect of the present invention, there is provideda method of producing an embedded semiconductor device substrate havinga semiconductor device integrated therein, comprising the steps of:forming a bump on an electrode portion on a surface of a semiconductordevice; disposing the semiconductor device in an opening formed on asubstrate; forming a conductive film on the semiconductor device and thesubstrate; integrating the semiconductor device and the substrate into asingle body; patterning the conductive film to form wiring patterns andremoving the conductive film on the semiconductor device to expose thebump; and forming a connection wiring pattern for connecting theelectrode portion on the semiconductor device and the wiring pattern.

In the present invention, it is preferred that the connection wiringpattern is formed by forming a connection wiring layer on the insulatingresin layer and the semiconductor device, patterning a resist materialformed on the connection wiring layer by performing direct exposure witha laser, and then performing etching.

Further, it is preferred that the connection wiring pattern is formed byforming a connection wiring layer on the insulating resin layer and thesemiconductor device, performing direct writing of a resist material onthe connection wiring layer, and then performing etching.

Moreover, it is preferred that the connection wiring pattern is formedby performing direct writing of a conductive material on the insulatingresin layer and the semiconductor device.

The above and other objects of the Invention will become more apparentfrom the following drawings taken in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an embedded semiconductor devicesubstrate according to Example 1 of the present invention.

FIGS. 2A, 2B, and 2C are cross-sectional views illustrating the steps ofProduction Method 1 of a semiconductor substrate according to Example 1of the present invention.

FIGS. 3A and 3B are cross-sectional views illustrating the steps ofProduction Method 1 of the semiconductor substrate according to Example1 of the present invention.

FIGS. 4A, 4B, and 4C are cross-sectional views illustrating the steps ofProduction Method 1 of the semiconductor substrate according to Example1 of the present invention.

FIGS. 5A and 5B are plan views illustrating the arrangement of bumps ofa semiconductor device and a connection wiring pattern according toExample 1 of the present invention.

FIGS. 6A and 6B are plan views illustrating the arrangement of bumps ofa semiconductor device and a connection wiring pattern according toExample 1 of the present invention.

FIGS. 7A, 7B, and 7C are cross-sectional views illustrating the steps ofProduction Method 2 of the semiconductor substrate according to Example1 of the present invention.

FIG. 8 is a cross-sectional view of an embedded semiconductor devicesubstrate according to Example 2 of the present invention.

FIGS. 9A and 9B are cross-sectional views illustrating the steps of aproduction method of a semiconductor substrate according to Example 2 ofthe present invention.

FIGS. 10A, 10B, 10C, 10D, 10E, and 10F are cross-sectional viewsillustrating the steps of a production method of a semiconductorsubstrate according to a conventional example.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will be explained.

EXAMPLE 1

FIG. 1 is a cross-sectional view of an embedded semiconductor devicesubstrate 20 according to Example 1 of the present invention. In thefigure, reference numeral 1 denotes a semiconductor device, andreference numeral 2 denotes a bump formed on an electrode portion 11 onthe semiconductor device 1. Portions other than the electrode portion 11on the semiconductor device 1 are covered with an insulating layer 13.Reference numeral 12 denotes a resin film provided on the insulatinglayer 13 and having a thickness which is approximately the same as theheight of the bump 2. An insulating layer 4 is provided under thesemiconductor device 1. Reference numeral 5 denotes an insulating resinlayer which forms a body of a printed wiring board. Reference symbol 3 adenotes a rear surface wiring pattern formed on a rear surface of theinsulating resin layer 5, and reference symbol 7 a denotes a frontsurface wiring pattern formed on a front surface of the insulating resinlayer 5. Reference numeral 6 denotes an adhesive resin layer which sealsthe semiconductor device 1. Reference symbol 10 a denotes a connectionwiring pattern which connects the front surface wiring pattern 7 a onthe insulating resin layer 5 and the bump 2 on the semiconductor device1. The connection wiring pattern 10 a connects the bump 2 and the frontsurface wiring pattern 7 a through a conductive protective layer 9 a.

(Production Method 1)

Next, a first method of producing the embedded semiconductor devicesubstrate 20 shown in FIG. 1 will be explained with reference to FIGS.2A to 4C. Firstly, as shown in FIG. 2A, bumps 2 are formed on theelectrode portion 11 on an upper surface of the semiconductor device 1.For the bumps 2, a metal such as Au or Cu or a solder is used. As to theshape thereof, a sphere or cylinder with a diameter of 20 to 30 μm isused. The upper surface of the semiconductor device 1 is covered withthe insulating layer 13, and only the electrode portion 11 is exposed tothe upper surface. An epoxy resin or the like can be used as theinsulating layer 13. Further, the resin film 12 having a thickness whichis approximately the same as the height of the bump 2 is formed in anactive area of the upper surface of the insulating layer 13 formed onthe upper surface of the semiconductor device 1. A polyimide film or thelike can be used as the resin film 12.

Next, the semiconductor device 1 having the bumps 2 and the resin film12 formed on the surface thereof, and the rear surface wiring layer 3are bonded through the insulating layer 4. As the insulating layer 4,there is used an epoxy resin film of 10 to 50 μm in thickness or thelike. As the rear surface wiring layer 3, it is possible to use a thinfilm such as of copper or aluminum of 10 to 35 μm in thickness. Thesemiconductor device 1 is bonded to the rear surface wiring layer 3through the insulating layer 4 by heat curing.

Subsequently, as shown in FIG. 2B, the insulating resin layer 5 whichhas approximately the same thickness as the thickness (50 to 150 μm) ofthe semiconductor device 1, and has the opening 5 a with a shapecorresponding to the shape of the semiconductor device 1 is disposed atsuch a location that the opening 5 a contains the semiconductor device1. As the insulating resin layer 5, a prepreg material containing glasscloth can be used. The semiconductor device 1 is disposed in the opening5 a of the insulating resin layer 5.

In addition, on the insulating resin layer 5 and semiconductor device 1,an RCC material 8 having the adhesive resin layer 6 such as of an epoxylined on the front surface wiring layer 7 is disposed. As the frontsurface wiring layer 7, similarly to the rear surface wiring layer 3, itis possible to use a thin film such as of copper or aluminum of 10 to 35μm in thickness. As the adhesive resin layer 6, an epoxy resin film witha thickness of 20 to 60 μm or the like can be used.

Next, as shown in FIG. 2C, the rear surface wiring layer 3, theinsulating resin layer 5, and the RCC material 8 are simultaneouslysubjected to heat pressing at a temperature of 150 to 200° C. in avacuum atmosphere. Thereby, the rear surface wiring layer 3, theinsulating resin layer 5, and the RCC material 8 are integrated into asingle substrate. Since the flowability of the adhesive resin layer 6becomes high by the heating, the adhesive resin is flown to enter a gapbetween the semiconductor device 1 in the opening 5 a and the insulatingresin layer 5 to fix the semiconductor device 1 securely. In addition,since the adhesive resin layer 6 on the bumps 2 is flown away by thebumps, the bumps 2 and the front surface wiring layer 7 come intocontact with each other.

At this time, the reason why the prepreg material 5 containing glasscloth is used is to prevent the flatness of the surface after the heatpressing from being impaired due to a difference in pressure between aportion where the semiconductor device 1 exists and a portion where nosemiconductor device exists generated by the pressure applied during theheat pressing. Also from this viewpoint, it is preferable that thethickness of the glass cloth is equal to or somewhat larger than the sumof the thickness of the semiconductor device 1 and the height of thebump 2.

In addition, the above-mentioned resin film 12 prevents the frontsurface wiring layer 7 on the semiconductor device 1 from becominguneven (non-flat) due to the bumps 2 provided on the semiconductordevice 1. Furthermore, when the bumps 2 deform to reduce their heightsto the thickness of the resin film 12, the resin film 12 also receivesthe applied pressure, so that it is possible to prevent thesemiconductor device 1 from being damaged by concentration of thepressing pressure on the bumps 2.

Next, as shown in FIG. 3A, the front surface wiring layer 7 and the rearsurface wiring layer 3 of the integrated substrate are patterned to formthe front surface wiring pattern 7 a and the rear surface wiring pattern3 a. Thereby, the top portions of the bumps 2 are exposed.

Subsequently, as shown in FIG. 3B, a protective layer 9 of 1 to 3 μmthick is formed on the front and the rear surfaces of the substrate byelectroless plating. As the protective layer 9, a metal such as Ni canbe used. The protective layer 9 plays roles of protecting the thusformed wiring pattern 7 a and of preventing diffusion between the bumps2 of the semiconductor device 1 and the connection wiring pattern 10 adescribed later.

Next, as shown in FIG. 4A, a connection wiring layer 10 of 1 to 3 μmthick is formed on the protective layer 9 by plating. A metal such as Cucan be used for the connection wiring layer 10.

Subsequently, the positions of the bumps 2 and the front surface wiringpattern 7 a are confirmed, and a resist R1 is formed in alignment withthose positions, as shown in FIG. 4B. Specifically, a negative resistlayer is provided on the surface on the side of which the bumps 2 of thesemiconductor device 1 are exposed, and the positions of the respectivebumps 2 are detected with respect to the individual semiconductordevices. After that, direct exposure with a light beam is performed toan area ranging from the region where the bump 2 is exposed to theelectrode portion of the wiring pattern 7 a to be connected. As thelight beam, any light may be used as long as it has a wavelength band inwhich the resist material is photosensitive, with UV light beinggenerally used. In addition, as a method of performing direct exposure,it is possible to provide an X-Y driving unit on a beam head, or toprovide an X-Y driving unit on a stage for holding the substrate andperform driving as programmed.

Incidentally, the resist pattern R1 can be formed, not only by formingonce a resist film on the entire surface and then performing directwriting with a laser as described above, but also by performing directwriting of a resist itself. By performing direct writing of the resistitself, it becomes possible to reduce the production steps.

Next, by performing exposure followed by development for the respectivesemiconductor devices 1, the resist pattern R1 is formed only onportions from the bumps 2 of the semiconductor device 1 to the electrodeportion of the wiring pattern 7 a. In this state, when the connectionwiring pattern layer 10 is etched with a persulfuric acid solution, aportion of the connection wiring pattern layer (Cu layer) 10 on theprotective layer (Ni layer) 9 other than the portion covered with theresist pattern R1 is removed. Thereby, the connection wiring patternlayer 10 is patterned to provide the connection wiring pattern 10 a. Atthis time, the etching conditions are adjusted so that the etchant doesnot etch the protective layer (Ni layer) 9.

Subsequently, in the state in which the resist pattern R1 remains, theprotective layer (Ni layer) 9 is etched. At this time, a ferric chloridebased solution is used as an etchant. Although the ferric chloride basedsolution also etches the connection wiring pattern 10 a, since theconnection wiring pattern 10a is far thicker than the protective layer9, the connection wiring pattern will not be disconnected. Inparticular, in the case of a very thin connection wiring pattern 10 a,it is possible to perform stable pattern formation since the Cu and theresist exist on the Ni.

Then, by stripping the resist pattern R1, as shown in FIG. 4C, theembedded semiconductor device substrate 20 can be obtained.

FIGS. 5A, 5B, 6A and 6B are plan views of the embedded semiconductordevice substrate 20 showing the connection wiring pattern 10 a whichconnects the bumps 2 and the wiring pattern 7 a. FIGS. 5A and 6A areviews showing the state before forming the connection wiring pattern 10a, and FIGS. 5B and 6B are views showing the state after forming theconnection wiring pattern 10 a. With respect to FIGS. 5A and 5B, inFIGS. 6A and 6B the semiconductor device 1 is disposed obliquely. Inthis example, in the step of forming the resist R1 shown in FIG. 4Bmentioned above, writing of the resist with a beam is performed whilepositions ranging from the bumps 2 of the semiconductor device 1 to theconnecting portions of the wiring pattern 7 a are correctedautomatically. Hence, even if the positional relationship between thebumps 3 of the semiconductor device 1 and the front surface wiringpattern 7 a deviates somewhat from the adequate one, it is possible toattain always stable connection.

According to the present invention, a process of forming the wiringpattern 7 a and a process of forming the connection wiring pattern 10 aare separated from each other. Thereby, it becomes possible to form theresist, when forming the connection wiring pattern 10 a, so as to be inalignment with the positions of the electrodes of the individualsemiconductor devices. Thereby, even if the positions of thesemiconductor devices are deviated from the adequate ones, since it ispossible to attend thereto by correcting the writing program, it ispossible to form easily such an extremely fine connection wiring pattern10 a having dimensions of wiring width/space=10 μm/10 μm to 20 μm/20 μm.

(Production Method 2)

Next, a second method of producing the embedded semiconductor devicesubstrate 20 shown in FIG. 1 will be explained with reference to FIGS.7A to 7C. In the second production method, a positive resist R2 is usedinstead of the negative resist R1 used in the first production method.In the second production method, the steps of the first productionmethod described with reference to FIGS. 2A to 3B are similarly carriedout as such, and then the steps shown in FIGS. 7A to 7C are carried outinstead of the steps shown in FIGS. 4A to 4C.

As shown in FIG. 7A, a positive resist R2 is formed so that onlyportions of the protective layer (Ni layer) 9 in which the connectionwiring pattern 10 a is to be formed is exposed. Then, electroplating isperformed by using the protective layer 9 as a common electrode layer toform the connection wiring pattern (Cu layer) 10 a. The thickness of theconnection wiring pattern (Cu layer) 10 a is preferably 5 to 15 μm.

Next, as shown in FIG. 7B, the resist pattern R2 is stripped, and asshown in FIG.7C, the protective layer 9 is etched. At that time,although the connection wiring pattern 10 a is also etched, since thefilm thickness thereof is larger than that of the protective layer 9,the film thickness becomes about 3 to 10 μm when etching is completed.Incidentally, the resist pattern R2 can be formed also by performingdirect writing of a resist itself as is the case with theabove-mentioned resist pattern R1. By performing direct writing of theresist itself, it becomes possible to reduce the production steps.

EXAMPLE 2

FIG. 8 is a cross-sectional view of an embedded semiconductor devicesubstrate 30 according to Example 2 of the present invention. Incomparison with the embedded semiconductor device substrate 20 ofExample 1 shown in FIG. 1, this example has such a structure that thereis no protective layer 9. In this example, the material of the bumps 2of the semiconductor device 1 is Ni. In this case, it is not necessaryto provide the protective layer 9 which functions as a diffusion barrierlayer between the bumps 2 and the wiring pattern 7 a. Incidentally, inFIG. 8, the elements which are the same as those shown in FIG. 1 areidentified by like reference numerals or symbols.

Next, the method of producing the embedded semiconductor devicesubstrate 30 shown in FIG. 8 will be explained with reference to FIGS.9A and 9B. In the production method of this example, the steps of thefirst production method described with reference to FIGS. 2A to 3B aresimilarly carried out as such, and then the steps shown in FIGS. 9A and9B are carried out instead of the steps shown in FIGS. 4A to 4C.

As shown in FIG. 9A, after forming the wiring patterns 3 a and 7 a, theconnection wiring pattern layer (Cu layer) 10 is formed on the entiresurface in a thickness of 3 to 10 μm by electroless plating. Then, theconnection wiring pattern layer 10 is etched using a negative resistpattern R3 to form the connection wiring pattern 10 a which is a verythin pattern as shown in FIG. 9B.

Incidentally, although in this example the bumps 2 are made of Ni andthe connection wiring pattern 10 a is made of Cu, the bumps 2 may bemade of Cu and the connection wiring pattern 10 a may be made of Ni.Furthermore, the bumps 2 may be made of Ni and the connection wiringpattern 10 a may also be made of Ni, or the bumps 2 may be made of Cuand the connection wiring pattern 10 a may also be made of Cu.

Incidentally, the resist pattern R3 can be formed also by performingdirect writing of a resist itself as is the case with theabove-mentioned resist pattern R1. By performing direct writing of theresist itself, it becomes possible to reduce the production steps.

Furthermore, it is also possible to perform direct writing of theconnection wiring pattern 10 a instead of the resist. Thereby, it ispossible to omit exposure and development process after writing of aresist.

According to the present invention, in an embedded semiconductor devicesubstrate, electrodes of a semiconductor device and a wiring pattern ona printed wiring board are connected by means of a connection wiringpattern. In addition, the connection wiring pattern is formed in aseparate step after burying the semiconductor device into the printedwiring board. Thereby, it becomes possible to form the connection wiringpattern corresponding to positions of the electrodes of thesemiconductor device and the patterned wiring on the printed wiringboard. In addition, it becomes possible to perform electric connectionwith a wiring pattern securely even when the electrode portion of thesemiconductor device has a narrow pitch.

Furthermore, when a semiconductor device is buried inside a substrateand a wiring pattern is formed, it becomes possible to performpost-process tests such as a burn-in test easily, so that non-defectiveproducts can be selected. Hence, even when further combined with othercomponents or devices, it is possible to maintain a high yield and toreduce the production cost.

Moreover, since the degree of freedom of wiring design is high, it ispossible to address combination with various semiconductor devices orelectric circuit components flexibly. Hence, it becomes possible toprovide higher-performance, small-size, and low-cost semiconductorproducts.

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims priority from Japanese Patent Application Nos.2005-318962 filed on Nov. 2, 2005 and 2006-291272 filed on Oct. 26,2006, which are hereby incorporated by reference herein.

1. An embedded semiconductor device substrate having a semiconductordevice integrated in an insulating resin layer, wherein a wiring patternis formed on the insulating resin layer, a bump for connection is formedon an electrode portion on the semiconductor device, and the wiringpattern and the bump are connected through a connection wiring patternprovided on the wiring pattern and the bump.
 2. The embeddedsemiconductor device substrate according to claim 1, wherein theconnection wiring pattern is thinner than the wiring pattern.
 3. Theembedded semiconductor device substrate according to claim 1, whereinthe wiring has a multi-layer structure which is comprised of a pluralityof materials.
 4. A method of producing an embedded semiconductor devicesubstrate having a semiconductor device integrated therein, comprisingthe steps of: forming a bump on an electrode portion on a surface of asemiconductor device; disposing the semiconductor device in an openingformed on an substrate; forming a conductive film on the semiconductordevice and the substrate; integrating the semiconductor device and thesubstrate into a single body; patterning the conductive film to formwiring patterns and removing the conductive film on the semiconductordevice to expose the bump; and forming a connection wiring pattern forconnecting the electrode portion on the semiconductor device and thewiring pattern.
 5. The method according to claim 4, wherein theconnection wiring pattern is formed by forming a connection wiring layeron the substrate and the semiconductor device, patterning a resistmaterial formed on the connection wiring layer by performing directexposure with a laser, and then performing etching by using the resistmaterial as an etching mask.
 6. The method according to claim 4, whereinthe connection wiring pattern is formed by forming an under layer of aconnection wiring layer on the substrate and the semiconductor device,patterning a resist material formed on the connection wiring layer byperforming direct exposure with a laser, and then performing plating byusing the resist material as a plating mask.
 7. The method according toclaim 4, wherein the connection wiring pattern is formed by forming aconnection wiring layer on the insulating resin layer and thesemiconductor device, performing direct writing of a resist material onthe connection wiring layer, and then performing etching.
 8. The methodaccording to claim 4, wherein the connection wiring pattern is formed byperforming direct writing of a conductive material on the insulatingresin layer and the semiconductor device.